With the increasing demand for electronic devices to have reduced current consumption, and to avoid the use of off-chip components, there has been an increasing trend for electronic devices to perform processing in the digital domain. Consequently, there has been an increasing demand for high-resolution, low-power, and inexpensive analog-to-digital converters (ADC).
One type of ADC that is commonly used for analog-to-digital conversion of signals is the over sampling ADC based upon delta-sigma Δ-Σ modulation. Over sampling ADCs use an over sampling ratio (OSR) that is the ratio of the sampling frequency of the delta-sigma modulator up to twice the bandwidth (Nyquist frequency) of the input signal. The over sampling ratio (OSR) is typically greater than one and will often be greater than a few tens. For conventional n-th order delta-sigma modulators (DSM), the signal to quantization noise ratio increases by n*6 dB+3 dB for each doubling of the OSR. Thus, better resolution is achieved by implementing a higher OSR.
Furthermore, multi-order modulators are arranged to provide noise shaping, such that the quantization noise is small in the frequency band of interest, and large elsewhere. For applications that operate with a low bandwidth, for example 20 kHz, a simple DSM, for example a 2nd order DSM, would be suitable for providing the required noise shaping.
However, more recently there has been a need to use ADCs in high bandwidth applications, such as cellular systems and wireless local area networks (WLAN). For example, a wireless wideband code division multiple access (WCDMA) handset may be required to operate with a bandwidth of the order of 2 MHz. For a low order DSM to provide the required analog to digital conversion for a high bandwidth signal, with the required noise shaping, a high OSR would be required that would not only be difficult to design but would also result in a high power consumption for the DSM.
Such a requirement is unacceptable for battery-powered applications or products, such as mobile phones. It is possible for a DSM to provide the required noise shaping characteristics for high bandwidth applications, with a reduced OSR, by increasing the order of the DSM. However, for the DSM to have the dynamic range required for high bandwidth applications it is desirable for the DSM to include, or at least to be combined with, an embedded parallel (i.e. flash) ADC having a 2-bit or greater number of bits quantizer. However, the use of a high bit flash ADC again results in high power consumption. For example, the power dissipation for a 6-bit quantizer may correspond to approximately a quarter of the total DSM power dissipation.
In the field of the present invention, the document ‘Multi-bit Delta-sigma ADC’, authored by C. Petrie and M. Miller, Motorola Data Converter Conference, July 2001: describes a 2nd order 6-bit DSM.
European Patent Application EP1800342 describes a mechanism for dynamic control of a number of active bits in a multi-bit quantizer. EP1800342 describes a windowing technique to turn off unnecessary comparators in the quantizer. By turning off some comparators the power dissipation is reduced but the die size remains unchanged. Furthermore, the technique is impractical with a low voltage supply, as are used by wireless communication units.
Thus, a need exists for an improved electronic device, and an integrated circuit (IC), comprising a multi-bit delta-sigma converter and method of operation therefor that minimizes power dissipation, die size and voltage supply requirements. It is also desirable to improve the stability of such a delta-sigma converter in a presence of large ‘out-of-band’ interfering signals.